1. Field of the Invention
The present invention relates generally to a differential detector imparted with an error correcting function, which detector is employed in a radio receiver of a digital mobile communication system for demodulating a differential phase modulated or shifted signal. More particularly, the present invention is concerned with a differential detector with the error correcting function for correcting a two-symbol differential detection signal by making use of a four-symbol differential detection signal and then correcting a one-symbol differential detection signal by utilizing the corrected two-symbol differential detection signal.
2. Description of Related Art
In digital mobile communication such as a digital cellular mobile phone system, there is used a differential phase-shifted signal such as a signal which has undergone .pi./4-DQPSK (.pi./4 differential quadrature phase shift keying) or the like. The differential phase-shifted signal can be detected by a synchronous detector or a differential detector. Although the circuit configuration of the differential detector is relatively simple, the differential detector suffers a higher bit error rate when compared with the synchronous detector. Under the circumstances, the differential detector with error correcting function is employed with a view to reducing the bit error rate.
For having better understanding of the concept underlying the present invention, description will first be made of a conventional differential detector with error correcting function. FIG. 8 of the accompanying drawings is a functional block diagram showing schematically a structure of a conventional differential detector with error correcting function. Referring to FIG. 8, a reference numeral 1 denotes a one-symbol differential detection circuit for performing phase comparison between a current input signal and an input signal preceding by one symbol relative to the current input signal to thereby output a phase difference signal, numeral 2 denotes a two-symbol differential detection circuit for performing phase comparison between a current input signal and an input signal preceding by two symbols relative to the current input signal to thereby output a phase difference signal, and numeral 3 denotes an error correction circuit. Further, FIG. 9 of the accompanying drawings is a functional block diagram showing schematically a typical structure of the one-symbol differential detection circuit 1.
In the differential detector with error correcting function implemented in such a configuration as shown in FIG. 8, the input signal 4 is inputted at first to the one-symbol differential detection circuit 1 to undergo phase comparison with the input signal preceding by one symbol (hereinafter also referred to as the one-symbol preceding input signal for convenience of the description), whereby a one-symbol differential detection signal 5 is obtained. In general, the one-symbol differential detection circuit 1 is composed of a delay circuit 8 for delaying the input signal 4 by one symbol and a digital multiplier 9, as shown in FIG. 9, wherein the one-symbol differential detection signal 5 can be derived by multiplying the current input signal 4 by the one-symbol preceding input signal.
Similarly, the input signal 4 is also inputted to the two-symbol differential detection circuit 2 to undergo phase comparison with the input signal preceding by two symbols (hereinafter also referred to as the two-symbol preceding input signal for convenience of the description), whereby a two-symbol differential detection signal 6 is obtained. In this conjunction, it should be mentioned that the two-symbol differential detection circuit 2 differs from the one-symbol differential detection circuit 1 in the respect that a delay circuit for delaying the input signal 4 by two symbols is provided in place of the delay circuit 8 designed for delaying the input signal 4 by one symbol and thus the two-symbol differential detection circuit 2 can be implemented in a circuit structure similar to that of the one-symbol differential detection circuit 1.
Finally, the one-symbol differential detection signal 5 and the two-symbol differential detection signal 6 are inputted to the error correction circuit 3, wherein the one-symbol differential detection signal 5 undergoes error correction processing, and thus an error-corrected differential detection output signal 7 is obtained, as can be seen from FIG. 8.
FIG. 10 of the accompanying drawings is a schematic circuit diagram showing a typical structure of the error correction circuit 3. In the figure, reference numerals 91 and 92 denote phase discrimination or decision circuits, respectively, numeral 12 denotes a digital adder, numerals 13, 14 and 17 denote digital subtractors, respectively, numerals 11 and 15 denote delay circuits, respectively, for delaying the input signal 4 by one symbol, and reference numeral 16 denotes a coincidence detection circuit.
Operation of the error correction circuit 3 will be described by reference to FIG. 10. In the first place, the phase of the one-symbol differential detection signal is discriminatively decided by means of the phase decision circuit 71, whereon the one-symbol differential detection signal 5 is delayed by one symbol by the delay circuit 11, whereby a delayed signal 18 is obtained. Representing by (n) the phase of the input signal 4, a phase difference signal D.sub.1 (n) corresponding to the one-symbol differential detection signal 5 and a delayed phase difference signal D.sub.1 (n-1) corresponding to the above-mentioned signal 18 can be given by the following expressions (1) and (2), respectively: EQU D.PHI..sub.1 (n)=.PHI.(n)-.PHI.(n-1) (1) EQU D.PHI..sub.1 (n-1)=.PHI.(n-1)-.PHI.(n-2) (2)
where n (=0, 1, 2 . . . ) indicate time points at which symbols make appearance, respectively.
Assuming that the one-symbol differential detection signal 5 contains error e(n), the above expression (2) can be rewritten as follows: EQU D.PHI..sub.1 (n-1)=.PHI.(n-1)-.PHI.(n-2)+e(n) (3)
In succession, the one-symbol differential detection signal 5 and the delayed signal 18 are added together by means of the digital adder 12, whereby a signal 19 is obtained. This signal 19 can be given by the following expression (4): ##EQU1##
On the other hand, a phase difference signal D.PHI..sub.2 (n) corresponding to the two-symbol differential detection signal 6 is given by the undermentioned expression (5) on the presumption that no error is contained in the two-symbol differential detection signal 6. EQU D.PHI..sub.2 (n)=.PHI.(n)-.PHI.(n-2) (5)
Subsequently, the two-symbol differential detection signal 6 having undergone the phase discrimination in the phase decision circuit 92 is subtracted from the signal 19 by means of the digital subtractor 13, as a result of which a signal s(n) corresponding to the output signal 20 of the digital subtractor 13 is obtained. The signal s(n) can be given by the following expression: EQU s(n)={.PHI.(n)-.PHI.(n-2)+e(n)}-{.PHI.(n)-.PHI.(n-2)}=e(n) (6)
Subsequently, a signal "error(n)" corresponding to an error pattern signal 23 is subtracted from the signal 20 by the digital subtractor 14, whereby a signal 21 which is free of influence of the error before one symbol is outputted from the digital subtractor 14 as a signal si(n). This signal si(n) is then delayed by one symbol by means of a delay circuit 15 whose output signal 22 is represented by si(n-1).
Now, the signals s(n) and si(n-1) corresponding to the signal 20 and the signal 22, respectively, are inputted to the coincidence detection circuit 16, whereby the signal "error(n)" is derived as the error pattern signal 23. The signal "error(n)" corresponding to the error pattern signal 23 is defined as follows: EQU error(n)=0 in case s(n)=si(n-1) 0 (7) EQU error(n)=0 in case s(n).noteq.0 and si(n-1)=0 (8) EQU error(n)=0 in case s(n)=0 and si(n-1).noteq.0 (9) EQU error(n)=m in case s(n)=si(n-1)=m.noteq.0 (10)
Finally, the error pattern signal 23 is subtracted from the signal 18 by the digital subtractor 17, whereby the error-corrected differential detection output signal 7 can be obtained.
With the arrangement of the conventional differential detector equipped with the error correcting function described above, the error correction can be performed for the one-symbol differential detection signal so far as no error exists in the two-symbol differential detection signal. However, when the two-symbol differential detection signal suffers error, the error correction can not be carried out correctly for the one-symbol differential detection signal, but erroneous correction of error will be performed, giving rise to a problems that error becomes more serious due to erroneous correction, whereby the bit error rate characteristic is degraded rather than improved.
In this conjunction, there is disclosed in Japanese Unexamined Patent Application Publication No. 8908/1979 (JP-A-54-8908) a differential detection error correcting scheme based on the concept underlying the error correction code in conjunction with the detection scheme for an m-value digital carrier transmission system such as of an m-phase differential phase shift keying (DPSK) scheme or an m-value continuous phase frequency shift keying (CPFSK) scheme. According to the differential detection error correcting scheme mentioned above, error detection as well as error correction can be performed by making use of the inherent redundancy that the symbol contained in the data for transmission represents a modulo-m sum value of the information symbol contained in the time slot relevant to the above-mentioned symbol and the information symbol preceding by one time slot. However, when two or more of four elements constituting the syndromes si(n) and si(n-1) suffer error, the error detection as well as the error detection are rendered impossible as in the case of the conventional differential detector described previously.